1. Field of the Invention
The present invention relates to a data transfer apparatus for transferring data from a main memory which is coupled to a main bus to a local memory which is coupled to a local bus.
2. Description of the Related Art
FIG. 6 shows the structure of a conventional data transfer apparatus 100.
The data transfer apparatus 100 transfers data from a main memory 112 to a local memory 156.
The data transfer apparatus 100 includes a main bus interface 127, a local bus interface 134, a DMA top address register 120, a DMA transfer word number register 121 for storing the number of words to be DMA-transferred, an adder 104, a subtracter 103, and a controller 122.
The main bus interface 127 and the local bus interface 134 are interconnected via an internal data line 151 and an internal address line 152.
The main bus interface 127 is coupled to a main data bus 113 and a main address bus 150. The main data bus 113 and the main address bus 150 are both coupled to peripheral devices for the data transfer apparatus 100, e.g., a CPU 110, a DMA controller 111, and a main memory 112.
The local bus interface 134 is coupled to a local data bus 128 and a local address bus 135. The local data bus 128 and the local address bus 135 are both coupled to peripheral devices for the data transfer apparatus 100, e.g., a local memory 156, via a bus interface 155.
An internal data processor 161 is further coupled to the local data bus 128 and the local address bus 135. The data transfer apparatus 100 and the internal data processor 161 are of a unified memory architecture sharing the local memory 156. The internal data processor 161 may be, for example, a video output processing circuit.
Herein, it is assumed that when transferring one word at a time from the CPU 110 and the DMA controller 111 to the local memory 156, the internal bus transfer cycle (or xe2x80x9clocal bus transfer cyclexe2x80x9d) may be xc2xd of the external bus transfer cycle (or xe2x80x9cmain bus transfer cyclexe2x80x9d).
In practice, however, the external bus transfer cycle and the internal bus transfer cycle may be 10 MHz and 100 MHz, respectively. One reason for this is that the clock of an internal bus of a chip is designed for a faster operation than the clock of an external bus of the chip.
In the present specification, any data transfer by the CPU 110 from the main memory 112 to the local memory 156 will be referred to as a xe2x80x9cCPU transferxe2x80x9d. Any data transfer by the DMA controller 111 from the main memory 112 to the local memory 156 will be referred to as a xe2x80x9cDMA transferxe2x80x9d.
The operation of the CPU 110, the DMA controller 111, and the data transfer apparatus 100 will be summarized below.
The main memory 112 and the local memory 156 are memory-mapped to the CPU 110 and the DMA controller 111.
The CPU 110 and the DMA controller 111, which alternately or consecutively acquire the right to use the main data bus 113, transfer data via the data transfer apparatus 100.
(CPU Transfer)
Once acquiring the right to use the main data bus 113, the CPU 110 reads data from the main memory 112 (as a xe2x80x9ctransfer sourcexe2x80x9d) via the main data bus 113 and the main address bus 150. The CPU 110 asserts a CPU access control signal 123 which is output to the data transfer apparatus 100, and outputs the data which has been read from the main memory 112 to the data transfer apparatus 100 (as a xe2x80x9ctransfer destinationxe2x80x9d) via the main data bus 113 and the main address bus 150.
(DMA Transfer)
In the case of a DMA transfer, it is necessary to utilize the CPU 110 to establish initial settings for DMA transfer in the DMA controller 111 and the data transfer apparatus 100.
First, a top address of the main memory 112 (which is the transfer source) and the number of words to be transferred are set in an internal register (not shown) of the DMA controller 111, and a request is made to begin a DMA transfer.
Next, through a CPU access, the CPU 110 sets a top address of the local memory 156 (which is the transfer destination) for DMA transfer, the top address being set in the DMA top address register 120 in the data transfer apparatus 100.
Next, through a CPU access, the CPU 110 sets the number of DMA transfers to be made in the DMA transfer word number register 121 in the data transfer apparatus 100.
As soon as the initial settings for DMA transfer are complete and the data transfer apparatus 100 becomes ready for data transfer to the local memory 156, the data transfer apparatus 100 asserts a DMA request signal 126.
Upon detecting the assertion of the DMA request signal 126 and acquiring the right to use the main data bus 113, the DMA controller 111 reads data from the main memory 112 (as a xe2x80x9ctransfer sourcexe2x80x9d) via the main data bus 113 and the main address bus 150. The DMA controller 111 asserts a DMA access control signal 125 which is output to the data transfer apparatus 100, and outputs the data which has been read from the main memory 112 to the data transfer apparatus 100 (as a xe2x80x9ctransfer destinationxe2x80x9d) via the main data bus 113.
During a DMA transfer, no address for the local memory 156 is output to the data transfer apparatus 100 as a transfer destination.
Next, the operations of the data transfer apparatus 100 and the bus controller 133 will be summarized below.
When performing a CPU transfer or a DMA transfer, the data transfer apparatus 100 outputs a local bus request signal 130 to the bus controller 133 for requesting a right to use the local data bus 128 and the local address bus 135, to which the local memory 156 (which is the data transfer destination) is coupled. Herein, it is assumed that the local data bus 128 and the local address bus 135 are shared by a plurality of processing blocks. In the case where a local bus request signal 160 has not been issued from the internal data processor 161, the bus controller 133 outputs a local bus grant signal 129 to the data transfer apparatus 100.
Next, the internal operation of the data transfer apparatus 100 will be described.
(CPU Transfer)
Data and a local memory address which are output from the CPU 110 along with the CPU access control signal 123 are temporarily stored in the main bus interface 127.
Upon receiving the CPU access control signal 123 from the CPU 110, the controller 122 asserts a wait control signal 124 which is output to the CPU 110, and outputs the local bus request signal 130 to the bus controller 133.
Upon receiving the local bus grant signal 129 from the bus controller 133, the controller 122 outputs a local bus control signal 162 to the local bus interface 134. In accordance with the local bus control signal 162, the local bus interface 134 outputs the data on the internal data line 151 to the local data bus 128, and outputs an address on the internal address line 152 to the local address bus 135.
The local bus control signal 162 includes a field which indicates the timing with which to output data on the local data bus 128 and an address selection field which indicates whether the address on the internal address line 152 or the address on the DMA address line 153 is to be output to the local address bus 135. In the case of a CPU transfer, the address selection field of the local bus control signal 162 is prescribed so that the address on the internal address line 152 is output to the local address bus 135.
The bus interface 155 decodes the address on the local address bus 135, and outputs the data on the local data bus 128 to the local memory 156 in accordance with the decoded address.
(DMA Transfer)
The controller 122 outputs the local bus request signal 130 to the bus controller 133.
If the local bus request signal 160 from the internal data processor 161 has not been asserted, the bus controller 133 outputs the local bus grant signal 129 to the controller 122.
Upon detecting the assertion of the local bus grant signal 129, the controller 122 outputs the DMA request signal 126 to the DMA controller 111. Upon receiving the asserted DMA access control signal 125 from the DMA controller 111, the controller 122 negates the DMA request signal 126, and outputs the local bus control signal 162 to the local bus interface 134. In the case of a DMA transfer, the address selection field of the local bus control signal 162 is prescribed so that the address on the DMA address line 153 is output to the local address bus 135.
In the case of a DMA transfer, the top address of the local memory 156 is previously set in the DMA top address register 120, and the number of words to be DMA-transferred is previously set in the DMA transfer word number register 121. In synchronization with the DMA access control signal 125, which is input as the DMA access begins, the controller 122 asserts a DMA start request signal 158.
Upon detecting the assertion of the DMA start request signal 158, the adder 104 increments the previous DMA address by one word, beginning from an initial value (i.e., the value stored in the DMA top address register 120), outputs the incremented DMA address to the DMA address line 153, and asserts a DMA address generation complete signal 154.
Upon detecting the assertion of the DMA start request signal 158, the subtracter 103 decrements the previous number of remaining words to be DMA-transferred by one word, beginning from an initial value (i.e., the value stored in the DMA transfer word number register 121). If the number of remaining words to be DMA-transferred is one, the subtracter 103 asserts a number-of-remaining-words to be DMA-transferred flag 157.
If no access is made by the CPU 110 when the data transfer to the local data bus 128 is completed, the controller 122 keeps asserting the DMA request signal 126 which is output to the DMA controller 111 until detection of the negation of the number-of-remaining-words to be DMA-transferred flag 157.
FIG. 7 illustrates an operation sequence of the data transfer apparatus 100 in the case where both CPU transfers and DMA transfers are performed.
In FIG. 7, it is assumed that the L (low) level of each signal corresponds to an asserted state of that signal, and the H (high) level of each signal corresponds to a negated state of that signal.
In the example illustrated in FIG. 7, a one-word CPU transfer is performed five times, and a ten-word DMA transfer is performed one time.
It is assumed that the aforementioned initial values for DMA transfer are set prior to a cycle T1. The data transfer apparatus 100 asserts the DMA request signal 126. Detecting the assertion of the DMA request signal 126, the DMA controller 111 asserts a DMA transfer request signal 197.
Now, it is also assumed that the CPU 110, although having detected the assertion of the DMA transfer request signal 197, will determine that a CPU transfer is to be made in the next and subsequent cycles. As a result, an external bus transfer (CPU_M1) between the CPU 110 and the data transfer apparatus 100 occurs during the cycles T1 and T2 (which cycles define a CPU basic access time). The CPU 110 begins to assert the CPU access control signal 123 in the cycle T1.
Upon detecting the assertion of the CPU access control signal 123, the data transfer apparatus 100 asserts the wait control signal 124. While the wait control signal 124 is being asserted, the CPU 110 is controlled so that neither a CPU transfer nor a DMA transfer can be made in the next and subsequent cycles.
In a cycle T3, an internal bus transfer (CPU_L1) occurs between the data transfer apparatus 100 and the local memory 156.
Once the internal bus transfer (CPU_L1) is completed, the data transfer apparatus 100 negates the wait control signal 124.
Upon detecting the negation of the wait control signal 124, the CPU 110 negates the CPU access control signal 123, and begins preparation for performing a CPU transfer or a DMA transfer in the next cycle. Herein, it is assumed that the CPU 110 detects the assertion of the DMA transfer request signal 197 and determines that a DMA transfer is to be made in the next cycle. In this case, the CPU 110 asserts a DMA transfer permission signal 196 which is output to the DMA controller 111.
Upon detecting the assertion of the DMA transfer permission signal 196, the DMA controller 111 performs an external bus transfer (DMA_M1) between the DMA controller 111 and the data transfer apparatus 100 with the cycles T1 and T2 defining a DMA basic access time, and asserts the DMA access control signal 125. The DMA access control signal 125 is asserted only during the DMA basic access time.
Upon detecting the assertion of the DMA access control signal 125, the data transfer apparatus 100 negates the DMA request signal 126.
In the cycle T6, an internal bus transfer (DMA_L1) occurs between the data transfer apparatus 100 and the local memory 156.
Once the internal bus transfer (DMA_L1) is completed, the data transfer apparatus 100 detects the number of remaining words to be DMA-transferred, and begins to assert the DMA request signal 126.
Upon detecting the assertion of the DMA request signal 126, the DMA controller 111 begins to assert the DMA transfer request signal 197.
Thereafter, the CPU 110 performs a CPU transfer or a DMA transfer in an alternate or consecutive manner. However, the internal bus transfer between the data transfer apparatus 100 and the local memory 156 must wait if any internal bus transfer (e.g., INT_1) is occurring between the internal data processor 161 and the local memory 156, until such an internal bus transfer is completed. As a result, more cycles are required to perform a data transfer between the CPU 110 and the data transfer apparatus 100.
In a cycle T7, the CPU 110 asserts the CPU access control signal 123, thereby instructing the data transfer apparatus 100 to start a data transfer. Upon detecting the assertion of the CPU access control signal 123, the data transfer apparatus 100 outputs the local bus request signal 130 to the bus controller 133, thereby requesting a right to use the local bus from the bus controller 133. In the example illustrated in FIG. 7, however, the bus controller 133 gives a right to use the local bus to the internal data processor 161, rather than the data transfer apparatus 100, because the internal data processor 161 has similarly requested a right to use the local bus.
In a cycle T8, an internal bus transfer (INT_1) between the internal data processor 161 and the local memory 156 begins. The internal bus transfer (INT_1) is continued until the end of a cycle T12.
At the end of the cycle T12, the bus controller 133 gives a right to use the local bus to the data transfer apparatus 100.
In a cycle T13, an internal bus transfer (CPU_L2) between the data transfer apparatus 100 and the local memory 156 occurs. Once the internal bus transfer (CPU_L2) is completed, the data transfer apparatus 100 negates the wait control signal 124. Upon detecting the negation of the wait control signal 124, the CPU 110 negates the CPU access control signal 123.
Thereafter, the CPU 110 and the DMA controller 111 compete with each other for a right to use the main buses so as to transfer data to the data transfer apparatus 100.
In a cycle T47, the DMA access control signal 125 is detected for a tenth time. At this point, the number of remaining words to be DMA-transferred reaches zero, so that the DMA request signal 126 from the data transfer apparatus 100 is negated. Thereafter, any DMA transfer will be resumed only after the aforementioned initial values for DMA transfer are again set by the CPU 110 in advance.
As described above, an internal bus transfer between the conventional data transfer apparatus 100 and the local memory 156 must wait until any internal bus transfer occurring between the internal data processor 161 and the local memory 156 is completed.
Thus, the conventional data transfer apparatus 100 is controlled so as to defer a CPU transfer, or to not output a DMA transfer request to the DMA controller 111, until the local bus becomes available. As a result, it is difficult to improve the overall data transfer rate of the entire system including the data transfer apparatus 100 and any peripheral devices associated therewith.
According to the present invention, there is provided a data transfer apparatus for transferring data from a main memory coupled to a main bus to a local memory coupled to a local bus, the data transfer apparatus including: a first-in-first-out buffer having a data region for storing one or more words of CPU access data which is accessed by a CPU coupled to the main bus, and a plurality of words of DMA access data which is accessed by a DMA controller coupled to the main bus; and a controller for controlling the first-in-first-out buffer, wherein, when the local bus is available, the controller controls the first-in-first-out buffer so as to consecutively transfer the one or more words of CPU access data stored in the data region to the local memory, and to burst transfer the plurality of words of DMA access data stored in the data region to the local memory.
In one embodiment of the invention, the controller executes local DMA transfers in units, where each unit comprises the plurality of words of DMA access data stored in the data region, and makes a request to use the local bus per unit of local DMA transfer.
In another embodiment of the invention, the controller executes the transfer of the one or more words of CPU access data stored in the data region in the form of a local DMA transfer, and the transfer of the plurality of words of DMA access data stored in the data region in the form of a local DMA transfer.
In still another embodiment of the invention, the first-in-first-out buffer further includes a region for storing information with which to determine whether the data stored in the data region is CPU access data or DMA access data.
Thus, the invention described herein makes possible the advantage of providing a data transfer apparatus which can improve an overall data transfer rate of an entire system including the data transfer apparatus itself and any peripheral devices associated therewith.